In the field of control, data distribution systems in which one controller controls a plurality of input/output units, arranged at positions away from the controller by several to several hundreds of meters, via a network have been widely put into practical use. Conventionally, the number of inputs and outputs per input/output unit (one unit is equal to one bit) ranges from 8 to 64. However, based on user demands, the number of inputs and outputs per input/output unit ranges from 1 to 8, in some recent input/output units. The network to be used is referred to as a field network for the former case, and as a sensor/actuator network for the latter case, due to the background of establishment in the market and a difference in the number of inputs and outputs of the input/output units. The technical standards for the field network and the sensor/actuator network have been published by government organizations and private organizations (Non-patent Literatures 1 to 6).
The outline of a conventional data distribution system will be explained with reference to FIGS. 1 to 13. In the specification, a network in which the number of inputs and outputs of the input/output unit is 8 or more is referred to as the field network, and a network in which the number of inputs and outputs of the input/output unit is less than 8 is referred to as the sensor/actuator network.
In the data distribution system used in the field of control, the controller controls the input/output information of several tens to several thousands inputs/outputs via the field network or the sensor/actuator network. That is, the controller monitors the input state of an input unit and controls the output state of an output unit. Therefore, as shown in FIG. 1, recent networks have been made hierarchical such that the inputs of from several hundreds to several thousands are divided into small groups of inputs of several tens, and data transmission within each group is performed via the sensor/actuator network.
FIG. 1 is a conceptual diagram when the field network and the sensor/actuator network are hierarchical. In FIG. 1, a controller 110 is connected to a field network 111 having a length of from several tens to several thousands of meters, and m groups (m=1 to M) are connected to the field network 111. A transfer apparatus 121m connected to the field network 111 is arranged in the group m. A plurality of input/output units 122 . . . are connected to the transfer apparatus 121m via a sensor/actuator network 112 having a length of from several to several hundreds of meters. That is, the transfer apparatus 121m transmits to the controller 110, input state data received from the input/output units 122 . . . belonging to its own group, and also distributes control data received from the controller 110 to the input/output units 122 . . . of its own group.
FIG. 2 is a diagram for explaining data distribution to the input/output units performed in one group shown in FIG. 1. FIG. 2 depicts a case that the controller 110 transmits onto the field network 111, a transmission frame 123m addressed to group m, for controlling the output state of the input/output unit 122mn in the group m, and the transfer apparatus 121m in the group m creates a transmission frame 123mn addressed to the input/output unit 122mn from the transmission frame 123m received from the field network 111, to transmit the data to the sensor/actuator network 112.
The transmission frame 123m is a bit string including a header field 71, a data field 72, and a check field 73. The transmission frame 123mn is a bit string including a header field 75, a data field 76, and a check field 77. The configuration of such a transmission frame is generally used in a serial communication, and the similar configuration is used in the Non-patent Literatures 1 to 6. The correspondence between the bit arrangement in the data field and the input/output ports of the input/output units is determined fixedly such that the least significant bit (LSB) represents the state of the 0-th input/output port.
The unit in the data field in the transmission frame specified in the Non-patent Literatures 1, 2, and 5 is 1 byte. The unit in the data field in the transmission frame specified in the Non-patent Literature 4 is 4 or 2 bytes. The unit in the data field in the transmission frame specified in the Non-patent Literature 3 is 0.5 byte (4 bits are fixed). The unit in the data field in the transmission frame specified in the Non-patent Literature 6 is 0.5 byte, 1 byte, or 2 bytes.
In FIG. 2, therefore, it is assumed that in the transmission frame 123m to be transmitted to the field network 111 by the controller 110, the unit in the data field 72 is 1 byte. Further, it is assumed that in the transmission frame 123mn to be transmitted to the sensor/actuator network 112 by the transfer apparatus 121m, the unit in the data field 76 is 1 byte. The one-to-one correspondence between the bit position in the data field and the input/output port is determined fixedly.
That is, the data field 72 in the transmission frame 123m includes 2×N bits (N is a multiple of 4), the first bit on the header field 71 side is the least significant bit (LSB), and the last bit on the check field 73 side is the most significant bit (MSB). In FIG. 2, it is shown that the input/output unit 122mn has two output ports mnP0 and mnP1, and hence, 2 bit data addressed to the respective input/output units 122mn is stored in the data field 72. In other words, the first and the second bits are data addressed to an input/output unit 122m1, and the third bit and the fourth bit are data addressed to an input/output unit 122m2.
In the transmission frame 123mn, the data field 76 includes 8 bits, the first bit b0 on the header field 75 side is the least significant bit (LSB), and the eighth bit b7 on the check field 77 side is the most significant bit (MSB).
The transfer apparatus 121m receives the transmission frame 123m, and fetches the (2×(m−1)+1)th bit to the (2×m)th bit in the data field 72 of the transmission frame 123m, in order to create the transmission frame 123mn, and stores these data in bits b0 to b1 in the data field 76 of the transmission frame 123mn, and stores “0” in bits b2 to b7. That is, in the depicted example, “00000001” is stored in the data field 76.
The input/output unit 122mn extracts the data field 76 from the transmission frame 123mn that is fetched from the sensor/actuator network 112, to determine the ON/OFF state of an output port mnPk (k=0, 1) according to the logical state of the first bit b0 and the second bit b1 in the data field 76. That is, in an output port mnP0, when b0=“1”, the output state is set to ON, and when b0=“0”, the output state is set to OFF. Likewise, in an output port mnP1, when b1=“1”, the output state is set to ON, and when b1=“0”, the output state is set to OFF. In the example shown in FIG. 2, since b0=“1” and b1=“0”, the output state of the output port mnP0 is ON, and the output state of the output port mnP1 is OFF.
The processing content in which the transfer apparatus 121m creates the transmission frame 123mn addressed to the input/output unit 122mn from the transmission frame 123m will be specifically explained with reference to FIGS. 3 and 4.
FIG. 3 illustrates a process in which the transfer apparatus 121m uses an 8-bit microcomputer to create the transmission frame 123mn to be distributed to an input/output unit 122m8 having a station number 8, from the transmission frame 123m. FIG. 4 is a diagram for explaining the processing content related to part “a” shown in FIG. 3.
In FIG. 3, the transfer apparatus 121m defines constants and variables, and after initializing the variables, obtains the value in the data field 72 in the transmission frame 123m according to a function get_field_network_data( ). The transfer apparatus 121m then stores d123m[1] from an array variable d123m, which is data addressed to station number 8, in a variable d123mn based on station number n=8. The transfer apparatus 121m then shifts the variable d123mn rightward (in a direction toward the LSB) by 6 bits, which is the number of bits obtained by multiplying 2 by 3, which is a surplus obtained by dividing “8-1” by 4, so that data addressed to the input/output unit 122m8 is stored in order of from the LSB of the variable d123mn. Lastly, AND operation of the variable d123mn and 0×03 (hexadecimal) is performed in order to set 0 into the bits storing no data. Thus, generation of data d123mn is complete, and the data d123mn is transmitted according to a function send_sensor_actuator_network( ).
In FIG. 4, the processing in part “a” shown in FIG. 3 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clock cycles is shown in column (C). As shown in column (C), as for the number of clock cycles required when the microcomputer executes a command, if one clock cycles is required for one command, in the case of station number n=8, a total of 45 clock cycles are required for the processing for 4 lines in the part “a” shown in FIG. 3, and 33 clock cycles are required for the bit shift processing.
A process in which the input/output unit 122m8 determines an output state mnPk from the transmission frame 123mn will be explained specifically with reference to FIGS. 5 to 7. FIGS. 5 and 6 illustrate a case that the input/output unit 122m8 uses an 8-bit microcomputer to determine the output state mnPk from the transmission frame 123mn. FIG. 5 depicts an example in which an output port has the same address, and FIG. 6 depicts an example in which the output port has a different address. FIG. 7 depicts details of the processing content relating to part “b” shown in FIG. 6.
In FIGS. 5 and 6, the input/output unit 122m8 defines a constant in a constant defining section, declares variables in a variable defining section, and then obtains the value in the data field 76 in the transmission frame 123mn according to a function get_sensor_actuator_network_data( ) into a variable d123mn. Based on the value of the low-order 2 bits in the variable d123mn, when the value is 1, the output state of the output port mnPk is turned ON, and when the value is 0, the output state of the output port mnPk is turned OFF.
In FIG. 7, the processing in part “b” shown in FIG. 6 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clock cycles is shown in column (C). As shown in column (C), as for the number of clock cycles required when the microcomputer executes a command, if one clock cycles is required for one command, a total of 12 clock cycles are required for the processing for the 2 lines in part “b” shown in FIG. 6.
FIG. 8 is a diagram for explaining the configuration of a conventional hierarchical data distribution system and contents of the process procedure of the transfer apparatus. FIG. 8 illustrates a case in which the controller 110, which controls the whole system, performs setting control of a state quantity output to an object to be controlled, to three input/output units 250q (q=A, B, C) via a transfer apparatus 211. As described above, the transfer apparatus 211 is connected to the controller 110 via the field network 111, and to the input/output units 250q via the sensor/actuator network 112. The configuration and the contents of the process procedure of the input/output units 250q shown in FIG. 8 are shown in FIGS. 9 to 11.
In FIG. 8, the transfer apparatus 211 includes a receiver 221, a dividing unit 222, a reception buffer 223, a specifying unit 224, an operation unit 225, and a transmitter 226. Upon receiving a transmission frame transmitted by the controller 110 via the field network 111, the receiver 221 extracts a bit string 113 including a data field, and provides the bit string to the dividing unit 222.
In FIG. 8, the bit string 113 includes 16 bits. The positions of the LSB and the MSB in the bit string 113 are displayed in the opposite direction to those shown in FIG. 2. In the bit string 113, the first and the second bits on the lowest order side indicate data 141A transmitted to the input/output unit 250q (q=A). The third to the sixth bits indicate data 141B transmitted to the input/output unit 250q (q=B). The seventh to the tenth bits indicate data 141C transmitted to the input/output unit 250q (q=C). The eleventh to the sixteenth bits, of which the sixteenth bit is the most significant bit, are not used.
The dividing unit 222 divides the bit string 113 received from the receiver 221 into data having a 1-byte length, and provides the data to the reception buffer 223 to store the data. In FIG. 8, since the bit string 113 includes 16 bits, the bit string 113 is divided into two, and hence, the reception buffer 223 stores a low-order data fragment 231a and a high-order data fragment 231b. 
The specifying unit 224 specifies data 141q to be transmitted to the input/output unit 250q, based on the low-order data fragment 231a and the high-order data fragment 231b stored in the reception buffer 223, and a station number q (q=A, B, C), and extracts a data fragment of 1 byte from the reception buffer 223, to provide it to the operation unit 225. In FIG. 8, four one-byte data fragments 131A, 131B, 131Cb, and 131Ca are extracted. The data fragment 131A includes the data 141A. The data fragment 131B includes the data 141B. The data fragment 131Ca includes low-order two bits of the data 141C, and the data fragment 131Cb includes high-order two bits of the data 141C.
The operation unit 225 generates a data fragment 132q to be sent to the input/output unit 250q, from a data fragment 131q extracted by the specifying unit 224. In FIG. 8, the operation unit 225 includes an AND circuit 225a to which the data fragment 131A is input, a shift register 225b to which the data fragment 131B is input, an AND circuit 225c to which the processing result by the shift register 225b is input, a shift register 225d to which the data fragment 131Ca is input, a shift register 225e to which the data fragment 131Cb is input, an OR circuit 225f to which the processing results by the shift registers 225d and 225e are input, and an AND circuit 225g to which the processing result by the OR circuit 225f is input.
The transmitter 226 stores the data fragment 132q generated by the operation unit 225 in a bit string 114q including a data field in the transmission frame, and transmits the bit string 114q to the sensor/actuator network 112.
As shown in FIGS. 9 to 11, the input/output unit 250q includes a receiver 251q, a data fragment storage unit 252q, and a comparator 253qr (r=0 to 3). Upon reception of the transmission frame transmitted by the transfer apparatus 211 via the sensor/actuator network 112, the receiver 251q extracts the bit string 114q including the data field therefrom, so that the bit string 114q is stored in the data fragment storage unit 252q. When the (r+1)th bit in the data stored in the data fragment storage unit 252q is “0”, the comparator 253qr sets an output state 254qr to OFF, and when the (r+1)th bit is “1”, sets the output state 254qr to ON.
The operation of the conventional data distribution system configured as described above will be explained below. In FIG. 8, the controller 110 sets a data field storing a bit string 113 (“1111111101010101” in the depicted example) including the data 141A (“01” in the depicted example) of two bits addressed to an input/output unit 250A, the data 141B (“0101” in the depicted example) of four bits addressed to an input/output unit 250B, and the data 141C (“1101” in the depicted example) of four bits addressed to an input/output unit 250C, in a transmission frame, and transmits the bit string 113 to the transfer apparatus 211 via the field network 111.
In the transfer apparatus 211, the receiver 221 extracts the bit string 113 including the data field. The extracted bit string 113 is divided by the dividing unit 222 into the low-order data fragment 231a including the low-order bytes “01010101” and the high-order data fragment 231b including the high-order bytes “11111111”, and both data fragments are stored in the reception buffer 223.
The low-order data fragment 231a stored in the reception buffer 223 includes the data 141A (“01”) to be transferred to the input/output unit 250A, the data 141B (“0101”) to be transferred to the input/output unit 250B, and half of the data 141C (low-order 2 bits “01”) to be transferred to the input/output unit 250C, and the high-order data fragment 231b includes the remaining half of the data 141C (high-order 2 bits “11”) to be transferred to the input/output unit 250C.
Therefore, the specifying unit 224 stores the low-order data fragment 231a in which the data 141A to be transferred to the input/output unit 250A is stored as the data fragment 131A to the operation unit 225. Further, the specifying unit 224 stores the low-order data fragment 231a in which the data 141B to be transferred to the input/output unit 250B is stored as the data fragment 131B to the operation unit 225. Since the data 141C to be transferred to the input/output unit 250C is included in the low-order data fragment 231a and the high-order data fragment 231b, the specifying unit 224 stores the low-order data fragment 231a and the high-order data fragment 231b, as the data fragments 131Ca and 131Cb to the operation unit 225.
When all the data 141q addressed to the input/output unit 250q is included in one data fragment 131q, the operation unit 225 performs shift operation with respect to the data fragment 131q so that the data 141q is stored in order from the LSB of the data fragment 132q, and performs AND operation with respect to the data fragment 131q so that bits other than the data 141q are set to “0”, to create the data fragment 132q to be sent to the transmitter 226.
On the other hand, when the data 141q is divided into two data fragments 131qa and 131qb, the data 141q is extracted from the data fragments 131qa and 131qb, to generate the data fragment 132q by performing the shift operation and OR operation so that the data 141q is stored in order of from the LSB of the data fragment 132q, to send the data fragment 132q to the transmitter 226, after setting bits other than the data 141q to “0”.
In other words, all the data 141A (“01”) addressed to the input/output unit 250A is included in the data fragment 131A (“01010101”) output by the specifying unit 224. Therefore, the operation unit 225 can determine from the station number A that the low-order 2 bits need only to be extracted from the data fragment 131A. In order to set the bits other than the data 141A to “0”, AND operation of the data fragment 131A (“01010101”) and a constant “00000011” is performed by the AND circuit 225a, and the obtained data “0000001” is sent to the transmitter 226 as a data fragment 132A. The transmitter 226 creates a transmission frame having a data field in which the data fragment 132A includes a bit string 114A, and transmits the transmission frame to the input/output unit 250A.
In the input/output unit 250A, a data fragment storage unit 252A stores the bit string 114A (“0000001”) extracted from the data field in the transmission frame received by a receiver 251A. A comparator 253A0 performs AND operation of the data “00000001” stored in the data fragment storage unit 252A and a constant “00000001”, and since the operation result is not “0”, sets an output 254A0 to ON. A comparator 253A1 performs AND operation of the data “00000001” stored in the data fragment storage unit 252A and a constant “00000010”, and since the operation result is “0”, sets an output 254A1 to OFF.
Further, in the operation unit 225, the data 141B (“0101”) addressed to the input/output unit 250B is included in the data fragment 131B (“01010101”) output by the specifying unit 224. Therefore, the operation unit 225 can determine from the station number B that the third to the sixth bits in the data fragment 131B need only to be extracted. In order to justify the bit position to the right end, the operation unit 225 provides the data fragment 131B to the shift register 225b, to shift the data bit rightward by 2 bits, to generate a data fragment 131B0 (“00010101”). In order to set bits other than the data 141B to “0”, AND operation of the data fragment 131B0 (“00010101”) and a constant “00001111” is performed by the AND circuit 225c, and the obtained data “0000101” is sent to the transmitter 226 as a data fragment 132B. The transmitter 226 creates a transmission frame having a data field in which the data fragment 132B includes a bit string 114B, and transmits the transmission frame to the input/output unit 250B.
In the input/output unit 250B, a data fragment storage unit 252B stores the bit string 114B (“00000101”) extracted from the data field in the transmission frame received by a receiver 251B. A comparator 253B0 performs AND operation of the data “00000101” stored in the data fragment storage unit 252B and the constant “00000001”, and since the operation result is not “0”, sets an output 254B0 to ON. A comparator 253B1 performs AND operation of the data “00000101” stored in the data fragment storage unit 252B and the constant “00000010”, and since the operation result is “0”, sets an output 254B1 to OFF.
A comparator 253B2 performs AND operation of the data “00000101” stored in the data fragment storage unit 252B and a constant “00000100”, and since the operation result is not “0”, sets an output 254B2 to ON. A comparator 253B3 performs AND operation of the data “00000101” stored in the data fragment storage unit 252B and a constant “00001000”, and since the operation result is “0”, sets an output 254B3 to OFF.
On the other hand, the data 141C (“1101”) addressed to the input/output unit 250C is divided into two, and included in the data fragment 131Ca (“01010101”) and the data fragment 131Cb (“11111111”) output by the specifying unit 224. Therefore, the operation unit 225 can determine from the station number C that the high-order 2 bits need only to be extracted from the data fragment 131Ca and the low-order 2 bits need only to be extracted from the data fragment 131Cb. In order to justify the bit position to the right end, the operation unit 225 provides the data fragment 131Ca to the shift register 225d, to shift the data bit rightward by 6 bits, to generate a data fragment 131C0 (“00000001”).
Further, as for the data fragment 131Cb, in order to justify the bit position at the right end to the position of the third bit, the operation unit 225 provides the data fragment 131Cb to the shift register 225e, to shift the data bit leftward by 2 bits, to generate a data fragment 131C1 (“11111100”). To store the data fragment 141C0 and the data fragment 141C1 in a 1-byte data fragment, OR operation of the data fragment 131C0 and the data fragment 131C1 is performed by an OR circuit 225f, to generate a data fragment 131C2 (“11111101”). In order to set the bits other than the data 141C (“1101”) to “0”, AND operation of the data fragment 131C2 (“11111101”) and a constant “00001111” is performed by the AND circuit 225g, and the result is sent to the transmitter 226 as a data fragment 132C (“0001101”). The transmitter 226 creates a transmission frame having a bit string 114c as a data field which includes the data fragment 132C, and transmits the transmission frame to the input/output unit 250C.
In the input/output unit 250C, a data fragment storage unit 252C stores the bit string 114C (“00001101”) extracted from the data field in the transmission frame received by a receiver 251C. A comparator 253C0 performs AND operation of the data “00001101” stored in the data fragment storage unit 252C and the constant “00000001”, and since the operation result is not “0”, sets an output 254C0 to ON. A comparator 253C1 performs AND operation of the data “00001101” stored in the data fragment storage unit 252C and the constant “00000010”, and since the operation result is “0”, sets an output 254C1 to OFF.
A comparator 253C2 performs AND operation of the data “00001101” stored in the data fragment storage unit 252C and the constant “00000100”, and since the operation result is not “0”, sets an output 254C2 to ON. A comparator 253C3 performs AND operation of the data “00001101” stored in the data fragment storage unit 252C and the constant “00001000”, and since the operation result is not “0”, sets an output 254C3 to ON.
With reference to FIGS. 12 and 13, a process in which the transfer apparatus 211 creates the data fragment 132q (q=A to C) from the bit string 113 will be specifically explained. FIG. 12 illustrates a case in which the transfer apparatus 211 uses an 8-bit microcomputer to execute the processing. FIG. 13 is a diagram for explaining the details of the process related to part “c” shown in FIG. 12. In FIG. 13, the process in part “c” shown in FIG. 12 is shown in column (A), a processing operation actually performed by the microcomputer is shown in column (B), and the required number of clock cycles is shown in column (C). As shown in column (C), as for the number of clock cycles required when the microcomputer executes a command, if one clock cycle is required for one command, a total of 99 clock cycles are required for the process in part “c” shown in FIG. 12.
The Non-patent Literatures mentioned above are as follows:
Non-patent Literature 1: JISB3511 Standard OPCN-1 (Standard for the field network published from a government organization).
Non-patent Literature 2: EN50170 Standard PROFIBUS (Standard for the field network published from a government organization).
Non-patent Literature 3: IEC62026-2 Standard AS-interface (Standard for the sensor/actuator network published from a government organization).
Non-patent literature 4: CC-Link by CC-Link Association (Standard for the field network published from a private organization).
Non-patent Literature 5: DeviceNet by ODVA (Standard for the field network published from a private organization).
Non-patent Literature 6: CC-Link/LT by CC-Link Association (Standard for the sensor/actuator network published from the private organization).
However, according to the conventional processing method, a bit shift operation is required when the transfer apparatus transfers data to the input/output unit, thereby causing a problem in that it takes time to perform processing for creating a transmission frame addressed to the input/output unit.
The time required until the transfer apparatus finishes processing for distributing data to all input/output units through the sensor/actuator network is calculated by multiplying the processing time for one unit by the number of input/output units. Therefore, there is a problem in that a delay in the processing due to the shift process causes performance deterioration in the distribution processing.
The present invention has been achieved in order to solve the above problems. It is an object of the present invention to provide a data distribution system, which does not require the bit shift operation by the transfer apparatus.